Controlled method of operating a programmable controller with a multi-level stage configuration

ABSTRACT

A controlled method of operating a programmable controller containing a program storage section including memory means in which a plurality of programs are stored with each program having a master reset flag and corresponding to a stage consisting of one or more control programs for performing control functions when the control programs in each stage are executed. In accordance with the method, a series of programs each corresponding to a stage is read out from the memory means with the control programs of each stage executed when both a master reset flag for a stage, which is reset in initialization, and a stage status corresponding to each of the read out stages meet a predetermined relationship. When executing a control program, a status for a subsequent macro-block is set or reset. The macro-block consists of a plurality of stages. When the status of the macro-block is set, the master reset flag for a stage is subsequently reset at the beginning of the macro-block. When the status of the macro-block is reset, the master reset flag for a stage is subsequently set at the beginning of the macro-block. A plurality of stages included in the macro-block are then executed provided that the status of the macro-block is set and the master reset flag for a stage is reset.

TECHNICAL FIELD

The present invention relates to a programmable controller, andparticularly relates to control on a system which is in a relationshipof subordination to a certain system.

BACKGROUND ART

In a conventional programmable controller (hereinafter abbreviated to"PC"), for example, as disclosed in Japanese Patent Post-ExaminationPublication No. Hei-1-50923, stage numbers, logical operations, dataoperation commands, timer commands, etc. have been provided so thatjudgment is made as to whether a status of a stage in question is set orreset so as to make control on every controlled unit specified by thestage.

However, in the case of controlling stages (lower-level stages) of asystem which is in a relationship of subordination to a certain stage(higher-level stage), for example, in the case where lower-level stagesare naturally reset when a higher-level stage is in a reset state, it isnecessary to provide commands to reset the respective lower-level stagesindividually. In that case, stage numbers of the lower-level stages haveno rules and are scattered, and the number thereof is so large that ithas been apt to make a mistake at the time of stating a command.Further, there has been a problem that it is difficult to understand therelationship of subordination at a glance of a program.

DISCLOSURE OF THE INVENTION

The present invention has been attained to solve the foregoing problemsand an object thereof is to provide a PC in which it is possible to makecontrol commands for lower-level stages easily, it is also possible tograsp a relationship of subordination, and it is further possible torealize a multi-level configuration.

According to an aspect of the present invention, the PC comprises astage table for storing statuses of respective stages and macro-blocksrespectively, an I/O table for storing input/output data, a register forstoring a master reset flag for a stage, a result register for storingresults of operation, a program storage unit for storing a user program,and an operation control unit for analyzing and executing the userprogram, the program storage unit storing at least a higher-levelprogram including the following commands (A) and (B), and programs for afirst lower-level macro-block including the following programs (C), (D)and (E):

(A) State commands SG each having a stage number stated therein and forobtaining an AND logic between an inverted signal of a master reset flagfor a stage and a status of a corresponding stage, and a group ofvarious commands each stated after a stage command SG, a program of eachof the various commands being executed when a status of thecorresponding stage is set;

(B) Macro stage commands MSG in each of which a stage number and amacro-block number are stated, and each of which is for obtaining an ANDlogic between an inverted signal of a master reset flag for a stage andthe status of the stage, and for setting a result of the ANDing into thestatus of the stage as well as into the status of the macro-block;

(C) Macro-label commands MLBL each of which is stated at the beginningof a program of a macro-block, and is for resetting a master reset flagfor a stage and for setting the status of the stage command SG statednext thereto when the status of the macro-block is set;

(D) Macro-end commands MEND each of which is stated at the end of aprogram of a macro-block, and is for resetting the status of themacro-block when the result register is set; and

(E) The command group of the commands (A) stated between the macro-labelcommands MLBL and the macro-end commands MEND.

In the PC according to another aspect of the present invention, theprograms for the first lower-level macro-block include the programs ofthe commands 1B), and the programs for a second lower-level macro-blockinclude the programs (C), (D) and (E). The status of a third macro-blockis controlled by the programs for the first lower-level macro-block.That is, a second lower-level macro-block controlled by the first-lowerlevel macro-block can be obtained, so that the programs are of athree-level configuration.

Further, in the PC according to another aspect of the present invention,the program storage unit stores programs for macro-blocks of a pluralityof lower-levels including contents similar to the programs for thesecond lower-level macro-block, and-the statuses of those lower-levelmacro-blocks are controlled by the program for a relatively highermacro-block so that it is possible to obtain a multi-level configurationhaving a desired number of levels.

In the above-mentioned PC, the status of the macro-block in the programof the first lower-level macro-block is controlled by the higher-levelprogram, and, further, a master reset flag for a stage is controlled bythe status of the first lower-level macro-block. For example, if thestatus of a macro-block is set, the master reset flag for tile stage ofthe macro-block is reset, so that operation control on the program ofthe macro-block is executed. Such a relationship between programs for ahigher-level macro-block and for a first lower-level macro-block is alsoestablished between programs for first and second lower-levelmacro-blocks. Such a relationship can be desiredly constituted, so thatit is possible to constitute a multi-level configuration easily.

Further, in the PC according to another-aspect of the present invention,the programs of respective levels are made to include a plurality ofmacro-stage commands MSG for controlling the programs of macro-blocks inlower levels, so that it is possible to use the programs of thelower-level macro-blocks as subroutines.

As has been described above, according to the present invention, lowerlevels are controlled by every macro-block by use of a stage command, anSGRST, a macro-stage command, a macro-label command and a macro-endcommand, and the every macro-block is controlled on the basis of amacro-stage command on a higher-level side, so that it is possible torealize a multi-level configuration easily, and it is possible to graspthe relationship of the multi-level configuration easily.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating a hardware structure of a PCwhich is an embodiment of the present invention;

FIG. 2 is a flowchart illustrating the operation of the PC;

FIG. 3 is a diagram illustrating a portion of a user program stored in auser program storage unit in FIG. 1;

FIG. 4 is a flowchart conceptually illustrating the operation of theprogram in FIG. 3;

FIG. 5 is a diagram illustrating each status when the user program inFIG. 3 is executed; and

FIGS. 6 and 7 are flowcharts conceptually illustrating the operations ofother embodiments of the present invention respectively.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram illustrating the configuration of the PCaccording to an embodiment of the present invention. In FIG. 1, thereference numeral 10 represents an operation control unit for processingvarious operations, and 12 represents a programmable counter forcounting on the basis of instructions from the operation control unit10. The reference numeral 14 represents a program storage unit in whichuser programs are stored, and from which a program having the addressassigned by a count value of the programmable counter 12 is read intothe operation control unit 10. The reference numeral 16 represents anI/O table for storing I/O statuses, in which input data i0, i1 . . . andoutput data Q1, Q2 . . . are stored. The reference numeral 18 representsan internal relay table for storing, for example, temporary data and soon. The reference numeral 20 represents a stage status table for storingstatuses of respective stages and macro-blocks, and 22 represents aregister for storing various data. The reference numeral 24 represents aresult register (hereinafter abbreviated to "RR") for temporarilystoring the results of operation of the operation control unit 10. Thereference numeral 26 represents a one-bit register for storing a masterreset flag for a stage.

The reference numeral 28 represents an input port for storing input datainto the I/O table through the operation control unit 10. The referencenumeral 30 represents an output port for outputting output data of theI/O table 16 through the operation control unit 10.

FIG. 2 is a flowchart illustrating the operation of the PC of FIG. 1. Asillustrated, first the operation control unit 10 performs initializationsuch as resetting of a master reset flag for a stage (hereinafterabbreviated to "SGRST"), and next performs input transfer. Herein theinput transfer means taking input data from an input module (not-shown)into the I/O table 16 through the input port 28. All the input data aretaken into the I/O table 16.

Next, the operation control unit 10 reads a program of the addressassigned by the programmable counter 12 from the program storage unit 14sequentially, analyzes the program, and performs various operations onthe basis of the result of analysis. For example, the operation controlunit 10 performs operation on the basis of input data of the I/O table16 or data of the data register 22, and stores the result of operationinto the I/O table 16 or the internal relay table 18.

Upon completion of the operation on all the user program, the operationcontrol unit 10 performs output transfer. Herein the output transfermeans supplying output data stored in the I/O table 16 to an outputmodule (not-shown) through the output port 30.

The operation control unit 10 repeats the above-mentioned inputtransfer, instruction execution and output transfer cyclically till anend command is given.

Various programs are executed in the program analysis and operationprocessing in the above-mentioned operation execution. Next, programspeculiar to the present invention will be described.

(A) Stage Command SG, iSG;

For example, SG S10

An AND logic between an inverted signal of the SGRST and a status ST ofa corresponding stage is obtained, and set into the status ST. In thisexample, the result of ANDing is set into a status ST of a stage S10.

In the command iSG, a status ST of a corresponding stage is set to "1"in advance at the time of initialization in FIG. 2, and the sameoperation as SG is performed at the time of executing the command.

(B) Macro Stage Command MSG;

For example, S11 M100

(1) An AND logic between an inverted signal of the SGRST and a status STof a corresponding stage is obtained, and set into the status ST. Inthis example, the result of ANDing is set into a status ST of a stageS11. (2) Further, the set content of the status ST is set into a statusST of a macro-block. In this example, the content of the status ST ofthe stage S11 is set into a status ST of a macro-block M100.

(C) Macro Label Command MLBL

For example, MLBL M100

When a status of a corresponding macro-block has been set to "1", theSGRST is reset, and a status ST of a stage of a stage command SG statednext is set to "1" at the same time. Further, when the status ST of thecorresponding macro-block has been reset, the SGRST is set to "1".

(D) Macro End Command MEND

When "1" has been set in the RR 24, a status ST of a correspondingmacro-block is reset.

FIG. 3 is a diagram in which a part of a user program stored in theprogram storage unit 14 is listed, and FIG. 4 is a diagram conceptuallyillustrating the user program.

(1) iSG S10; By this command iSG, an AND logic between an inverted logicof the SGRST and the status ST of the stage S10, which has been set to"1" in advance by the initialization, is obtained, and set into thestatus ST of the stage S10. Herein since the SGRST has been reset by theinitialization after turning-on of a power supply, "1" is set into thestatus ST of the stage S10.

(2) LD iO; By this command LD, the input data i0 of the I/O table 16 isstored into the RR 24.

(3) JMP S11; In this command JMP, nothing is processed when the RR 24has been reset. When "1" has been set in the RR 24, a status ST of astage including this command JMP (the status of the stage S10 herein) isreset, and "1" is set into a status ST of a stage to be an operand ofthe command JMP (the status of the stage S11 herein) at the same time.

For example, assume now "1" has been set in the input data i0 in theabove-mentioned processing, and the RR 24 is in the state of being setto "1", so that the command JMP is effective, the status ST of the stageS10 is reset, and "1" is set into the status ST of the stage S11.

(4) MSG S11 M100;

Herein since the status ST of the stage S11 has been set to "1", and theSGRST has been reset, the AND logic between an inverted signal of theSGRST and the status ST of the stage S11 becomes "1", so that "1" is setinto the status ST of the stage S11. Further, "1" is set into the statusST of the macro-block M100 on the basis of the content ("1") of thestatus ST of the stage S11.

If the AND logic between the inverted signal of the SGRST and the statusST of the stage S11 is "0", the status ST of the stage S11 is reset, andthe status ST of the macro-block M100 is also reset.

Although the program is executed sequentially thereafter, thedescription of a part of the program processed thereafter will beomitted, and the description about the program of a macro-block in theright of FIG. 3 will be continued.

(5) MLBL M100;

Since the status ST of the macro-block M100 has been changed from "0" to"1", the SGRST is reset thereby, and "1" is set into a status ST of astage of a stage command described in the next address, that is, thestage S100 herein. Consequently the processing on the stage S100 et seq.is made possible, and is performed in the same manner as mentionedabove. The description is therefore omitted.

If the status ST of the macro-block M100 has been reset, the SGRST isset. When the SGRST has been set, the statuses ST of SG100 et seq. arereset, so that commands of the stage command SG100 et seq. stated in thenext address are left without being executed. In this example, the stagecommands of stages S100 to S102 are not executed.

(6) MEND

When "1" has been set in the RR 24, the status ST of the presentmacro-block is reset. Consequently the processing of this macro-block isfinished. In this example, when the previous command "LD i4" isexecuted, the status ST of the macro-block is reset in-the conditionthat input data i4 of the I/O table 16 has been set to "1".

FIG. 5 is a diagram illustrating input data and data of respectiveportions when the program in FIG. 3 is executed, and the descriptionthereof will be made more specifically in the order of respectivescannings.

(1) Scanning (1);

By the command iSG S10, the status ST of the stage S10 has been set to"1" in advance by the initialization. Assume there is no input data atthis time.

(2) Scanning (2);

If "1" has been set in the input data i0 of the I/O table 16, thecommand "JMP S11" is executed to reset the status ST of the stage S10,and "1" is set into the status ST of the stage S11. Then the command"MSG S11 M100" is processed. By this processing, "1" is set into thestatus ST of the macro-block M100. And "1" is set into the status ST ofthe stage S100 by the command "MLBL M100".

(3) Scanning (3);

At the time of this scanning, "1" has been set in the respectivestatuses ST of the stages S11 and S100, and "1" is left as it is set inthe status ST of the macro-block M100. In this state, if "1" is set intothe input data i2 of the I/O table 16, processing is performed asfollows.

Since "1" is left as it is set in the statuses ST of the stage S11 andthe macro-block M100 and "1" has been set in the input data i2, "1" hasbeen set into the RR 24 by the command "LD i2". Therefore, by thecommand "JMP S101", the status ST of the stage S100 is reset, and "1" isset into the status ST of the stage S101.

Further, by the command "OUT Q11", the content of the RR 24 is suppliedto the output data Q11 of the internal relay table 18, and "1" is setinto the output data Q11 at this time.

(4) Scanning (4);

When the input data i2 of the I/O table 16 is reset and "1" is set intothe input data i3, the status ST of the stage S11 is left to be set, andthe status ST of the macro-block M100 is also left to be set, but the RR24 is reset by executing the command "LD i2".

Further, since the input data i3 has been set to "1", "1" is set intothe RR 24 by the command "LD i3", the status ST of the stage S101 isreset by the command "JMP S102", and the status ST of the stage S102 isset to "1".

(5) Scanning (5);

Due to the changing of the SG101 from "1" to "0", the RR 24 is reset,and the output data Q11 is reset by the command "OUT Q11".

(6) Scanning (6);

When the input data i4 is set, "1" is set into the RR 24 by the command"LD i4". Consequently the command "MEND" is executed, and the status STof this macro-block M100 is reset.

(7) Scanning (7);

Since "1" has been set in the status ST of the stage S11, and "0" hasbeen set in the status ST of the macro-block M100 in the previousscanning, "1" is set into the RR 24 by the command "LDN M100", thestatus ST of the stage S11 is reset by the command "JMP S12", and "1" isset into the status of the stage S12. Then, since the status of themacro-block M100 has changed from "1" to "0" in the execution on thecommand "MLBL M100" in this scanning, "1" is set into the SGRST.Therefore, operation on the respective stages of the stage S100 of themacro-block et seq. are not processed.

As has been described, the status ST of the macro-block M100 is set orreset by a higher-level program such as the command "MSG S11 M100" orthe like, and the SGRST is reset or set thereby, so that starting orstopping of the macro-block is controlled.

Although a two-level configuration is described in the above-mentionedembodiment, it is possible to provide a multi-level configuration morethan two levels in the same manner.

FIG. 6 is a conceptual diagram of another embodiment of the presentinvention. An (n+1)-level configuration is provided in this embodiment,in which for example, if "1" is set into a status ST of a macro-blockM100 by a command "MSG S11 M100" in the highest-level, the macro-blockM100 lower in level than it is made to perform operation, or if thestatus ST of the macro-block M100 is reset the operation of themacro-block M100 is forbidden.

In this macro-block M100, if "1" is set into a status ST of amacro-block M200 by the command "MSG S103 M200", the lower-levelmacro-block M200 is made to perform operation, and if the status ST ofthe macro-block M200 is reset, the operation of the macro-block M200 isforbidden.

As has been described above, a macro-block positioned in a relativelyhigher level can control the operation of macro-blocks positioned inlevels lower than the first-mentioned macro-block. In the embodiment ofFIG. 6, if the status ST of the stage S11 is reset to reset the statusST of the macro-block M100, all the statuses of macro-blocks lower inlevels than the macro-block M100 are reset, and their operations are notperformed.

FIG. 7 is a conceptual diagram of another embodiment of the presentinvention. A macro-block M100 is used as a subroutine in thisembodiment. If "1" is set into a status of a stage S11, "1" is also setinto the status of the macro-block M100, so that the operation of themacro-block M100 is executed. On the contrary, if the status ST of thestage S11 is reset, the status ST of the macro-block M100 is also resetso that the operation of the macro-block M100 is forbidden to beexecuted. Such processing is performed also in a stage S13 in the samemanner.

We claim:
 1. A controlled method for operating a programmable controllercontaining a program storage section including memory means in which aplurality of programs are stored with each program including a stagehaving a master reset flag and consisting of one or more controlprograms and a macro-block consisting of a plurality of stages, saidmethod comprising the steps of:reading out from said memory means aseries of said programs corresponding in a direct relationship to aplurality of said stages designated by stage number in a controllingunit and in a predetermined sequence for performing control functionswhen the control programs in each stage are executed, detecting therelationship between the master reset flag for each stage and the stagestatus, and executing the control programs in each stage upon detectingthe condition when the master reset flag for each stage is reset and thestage status is set.
 2. A controlled method for operating a programmablecontroller as defined in claim 1 further including a plurality ofmacro-blocks with each macro-block having a macro-block status flag,said method further comprising the steps of:setting or resetting amacro-block status flag corresponding to a subsequent macro-block for aplurality of stages following the eventual program being read out fromsaid memory means; resetting said master reset flag for the stageidentifying the beginning of said subsequent macro-block on thecondition that said subsequent macro-block is set, and setting saidmaster reset flag for the stage at the beginning of the subsequentmacro-block on the condition that said subsequent macro-block status isreset; and executing the plurality of stages included in the subsequentmacro-block when said status for said subsequent macro-block is set andsaid master reset flag for said stage is reset.
 3. A controlled methodof operating a programmable controller as defined in claim 2 containinga plurality of said macro-blocks with each consisting of a plurality ofstages further comprising the steps of:resetting or setting said masterreset flag for a stage at the beginning of another macro-block followingin succession from said subsequent macro-block on the condition that thestatus of said another macro-block is set or reset while the pluralityof stages included in the previous macro-block are being executed;executing a plurality of stages included in said another macro-blockwhen the status for said another macro-block is set and said masterreset flag for a stage is reset.